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PI7C7100 Datasheet(PDF) 58 Page - Pericom Semiconductor Corporation |
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PI7C7100 Datasheet(HTML) 58 Page - Pericom Semiconductor Corporation |
58 / 132 page 50 09/18/00 Rev 1.1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456 PI7C7100 3-Port PCI Bridge ADVANCE INFORMATION 10. Clocks This chapter provides information about the clocks. 10.1 Primary Clock Inputs PI7C7100 implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock. The secondary clock is derived internally from the primary clock, P_CLK, through an internal PLL. PI7C7100 operates at a maximum frequency of 33 MHz. 10.2 Secondary Clock Outputs PI7C7100 has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as clock inputs for up to sixteen external secondary bus devices. The S_CLKOUT[15:0] outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: • Each secondary clock output is limited to no more than one load. |
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