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IN74AC373 Datasheet(PDF) 4 Page - Integral Corp.

Part No. IN74AC373
Description  Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS
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Maker  INTEGRAL [Integral Corp.]
Homepage  http://www.iksemi.com/
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IN74AC373 Datasheet(HTML) 4 Page - Integral Corp.

   
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IN74AC373
419
AC ELECTRICAL CHARACTERISTICS(C
L=50pF,Input tr=tf=3.0 ns)
VCC
*
Guaranteed Limits
Symbol
Parameter
V
25
°C-40°C to
85
°C
Unit
Min
Max
Min
Max
tPLH
Propagation Delay, Input D to Q
(Figure 1)
3.3
5.0
1.5
1.5
13.5
9.5
1.5
1.5
15.0
10.5
ns
tPHL
Propagation Delay, Input D to Q
(Figure 1)
3.3
5.0
1.5
1.5
13.0
9.5
1.5
1.5
14.5
10.5
ns
tPLH
Propagation Delay, Latch Enable to Q (Figure
2)
3.3
5.0
1.5
1.5
13.5
9.5
1.5
1.5
15.0
10.5
ns
tPHL
Propagation Delay, Latch Enable to Q (Figure
2)
3.3
5.0
1.5
1.5
12.5
9.5
1.5
1.5
14.0
10.5
ns
tPZH
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
1.5
1.5
11.5
8.5
1.0
1.0
13.0
9.5
ns
tPZL
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
1.5
1.5
11.5
8.5
1.0
1.0
13.0
9.5
ns
tPHZ
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
1.5
1.5
12.5
11.0
1.0
1.0
14.5
12.5
ns
tPLZ
Propagation Delay, Output Enable to Q
(Figure 3)
3.3
5.0
1.5
1.5
11.5
8.5
1.0
1.0
12.5
10.0
ns
CIN
Maximum Input Capacitance
5.0
4.5
4.5
pF
Typical @25
°C,V
CC=5.0 V
CPD
Power Dissipation Capacitance
40
pF
*Voltage Range 3.3 V is 3.3 V
±0.3 V
Voltage Range 5.0 V is 5.0 V
±0.5 V
TIMING REQUIREMENTS(C
L=50pF,Input tr=tf=3.0 ns)
VCC
*
Guaranteed Limits
Symbol
Parameter
V
25
°C-40°C to
85
°C
Unit
tsu
Minimum Setup Time, Input D to Latch
Enable (Figure 4)
3.3
5.0
5.5
4.0
6.0
4.5
ns
th
Minimum Hold Time, Latch Enable to
Input D (Figure 4)
3.3
5.0
1.0
1.0
1.0
1.0
ns
tw
Minimum Pulse Width, Latch Enable
(Figure 2)
3.3
5.0
5.5
4.0
6.0
4.5
ns
*Voltage Range 3.3 V is 3.3 V
±0.3 V
Voltage Range 5.0 V is 5.0 V
±0.5 V


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