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74LVC1G74 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LVC1G74
Description  Single D-type flip-flop with set and reset; positive edge trigger
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC1G74 Datasheet(HTML) 2 Page - NXP Semiconductors

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2005 Feb 01
2
Philips Semiconductors
Product specification
Single D-type flip-flop with set and
reset; positive edge trigger
74LVC1G74
FEATURES
• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant inputs for interfacing with 5 V logic
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 V to 1.95 V)
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V).
•±24 mA output drive (VCC = 3.0 V)
• ESD protection:
– HBM EIA/JESD22-A114-B exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Multiple package options
• Specified from −40 °C to +85 °C and −40 °C to +125 °C.
DESCRIPTION
The 74LVC1G74 is a high-performance, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC1G74 is a single positive edge triggered D-type
flip-flop with individual data (D) inputs, clock (CP) inputs,
set (SD) and (RD) inputs, and complementary Q and Q
outputs.
This device is fully specified for partial power down
applications using Ioff. The Ioff circuitry disables the output,
preventing damaging backflow current through the device
when it is powered down.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly
tolerant to slower input rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay
CP to Q, QCL = 50 pF; VCC = 3.3 V
3.5
ns
SD to Q, QCL = 50 pF; VCC = 3.3 V
3.0
ns
RD to Q, QCL = 50 pF; VCC = 3.3 V
3.0
ns
fmax
maximum clock frequency
CL = 50 pF; VCC = 3.3 V
280
MHz
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance
VCC = 3.3 V; notes 1 and 2
15
pF


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