SC16C2550BIB48 datasheet(11/42 Pages) PHILIPS

Part #	SC16C2550BIB48

Description	5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors

SC16C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Product data

Rev. 02 — 14 December 2004

11 of 42

9397 750 14449

6.3 FIFO operation

The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control

Register (FCR) bit 0. The user can set the receive trigger level via FCR bits 6-7, but

not the transmit trigger level. The receiver FIFO section includes a time-out function

to ensure data is delivered to the external CPU. An interrupt is generated whenever

the Receive Holding Register (RHR) has not been read following the loading of a

character or the receive trigger level has not been reached.

6.4 Hardware/software and time-out interrupts

The interrupts are enabled by IER[0-3]. Care must be taken when handling these

interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the

SC16C2550B will issue a Transmit Holding Register interrupt. This interrupt must be

serviced prior to continuing operations. The ISR register provides the current singular

highest priority interrupt only. A condition can exist where a higher priority interrupt

may mask the lower priority interrupt(s). Only after servicing the higher pending

interrupt will the lower priority interrupt(s) be reﬂected in the status register. Servicing

the interrupt without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the

number of characters have reached the programmed trigger level. In this case, the

SC16C2550B FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The

time-out counter is reset at the center of each stop bit received or each time the

receive holding register (RHR) is read. The actual time-out value is 4 character time,

including data information length, start bit, parity bit, and the size of stop bit, i.e., 1

×,

1.5

×, or 2× bit times.

Table 5:

Flow control mechanism

Selected trigger level (characters)

INT pin activation

11

44

88

14

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