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CY62127DV30
MoBL®
Document #: 38-05229 Rev. *D
Page 4 of 12
AC Test Loads and Waveforms[8]
Data Retention Waveform[10]
Notes:
7. Tested initially and after any design or proces changes that may affect these parameters.
8. Test condition for the 45-ns part is a load capacitance of 30 pF.
9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 200 µs.
10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the Chip Enable signals or by disabling both.
Capacitance[7]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
8pF
COUT
Output Capacitance
8
pF
Thermal Resistance
Parameter
Description
Test Conditions
FBGA TSOP II Unit
θJA
Thermal Resistance (Junction to Ambient)[7]
Still Air, soldered on a 3 x 4.5 inch,
two-layer printed circuit board
55
76
°C/W
θJC
Thermal Resistance (Junction to Case)[7]
12
11
°C/W
Data Retention Characteristics
Parameter
Description
Conditions
Min.
Typ.[4]
Max.
Unit
VDR
VCC for Data Retention
1.5
V
ICCDR
Data Retention Current
VCC=1.5V, CE > VCC − 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V
L4
µA
LL
3
tCDR[7]
Chip Deselect to Data
Retention Time
0ns
tR[9]
Operation Recovery Time
200
µs
VCC Typ
VCC
OUTPUT
R2
C = 50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
OUTPUT
VTH
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Rise Time:
1 V/ns
Fall Time:
1 V/ns
L
Parameters
3.0V (2.7– 3.6V)
Unit
R1
1103
Ω
R2
1554
Ω
RTH
645
Ω
VTH
1.75
V
2.5V (2.2– 2.7V)
16600
15400
8000
1.2
tCDR
VDR > 1.5V
DATA RETENTION MODE
tR
CE or
VCC
BHE. BLE
VCC(min.)
V CC(min.)
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