10 / 30 page
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 10 of 30
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Suspend Read
Current
0
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
0
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
0
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
0
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
0
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
0
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
0
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
0
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
1
X
X
X
X
X
X
X
Hi-Z
X
Cycle Descriptions (continued)[1, 2, 3, 4]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode
standby current
ZZ > VDD – 0.2V
TBD
mA
tZZS
Device operation to
ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
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