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PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 7 of 30
Pin Configurations (continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
123456789
11
10
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DPd
DPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DPa
DPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DPe
DQe
DQe
DQe
DQe
AADSP
ADV
A
NC
NC
A
AA
A
A
AA
AA
A
A1
A0
A
AA
AA
A
NC
NC
NC
GW
NC
NC
BWSb
BWSf
BWSe
BWSa
BWSc
BWSg
BWSd
BWSh
TMS
TDI
TDO
TCK
NC
NC
MODE
NC
VSS
VSS
NC
CLK
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VDD
NC
OE
CE3
CE1
CE2
ADSC
BW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
VSS
NC
VDDQ
VSS
VSS
NC
VSS
VSSQ
VSS
VSS
VSS
VSS
NC
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
209-ball BGA (This package is offered on opportunity basis)
CY7C1487V33 (1M x72)
Pin Definitions
Pin Name
I/O
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0]
feed the two-bit counter.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d,e,f,g,h and
BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
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