NB7N017M

http://onsemi.com

3

Table 1. PIN DESCRIPTION

Pin Name

I/O

Default

State

Single/Differential

(Notes 1 and 2)

Description

CLK

ECL, CML, LVCMOS,

LVDS, LVTTL Input

−

Differential

Clock

CE

ECL, CML, LVCMOS,

LVDS, LVTTL Input

−

Differential

Clock Enable

MR

CMOS, ECL Input

Low

Single

Asynchronous Master Reset: Counter set to 0000 0000 to

reload at next CLK pulse, REGa and REGb = 1111 1111 and

TC = 1.

SEL

ECL, CML, LVCMOS,

LVDS, LVTTL Input

−

Differential

Divide Select

PLa, PLb

CMOS, ECL Input

Low

Single

Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level

Triggered)

TC

CML Output

−

Differential

Terminal Count, 16 mA CML output with 50 W Source

Pa[0:7], Pb[0:7]

CMOS, ECL Input

High

Single

Counter Program Pins. CMOS and PECL/NECL compatible

Pa7 = MSB, Pb7 = MSB

Power

−

−

Positive Supply

Power

−

−

Negative Supply

VTCLK, VTCLK,

VTSEL, VTSEL

VTCE, VTCE

Termination

−

Differential

50 W Internal Input Termination Resistor (Note 6)

Output

−

−

CMOS/ECL Reference Voltage Output

NC

N/A

−

−

No Connect (Note 4)

EP

−

−

−

Exposed Pad (Note 3)

1. All high speed inputs and outputs are differential to improve performance.

2. All single−ended inputs are CMOS and NECL/ECL compatible.

exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Exposed pad is bonded to the lowest

4. The NC pins are electrically connected to the die and must be left open.

6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied

then the device will be susceptible to self−oscillation.