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NT6DM32M16BD Datasheet(PDF) 20 Page - Nanya Technology Corporation. |
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NT6DM32M16BD Datasheet(HTML) 20 Page - Nanya Technology Corporation. |
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20 / 81 page  LPDDR 512Mb SDRAM NT6DM32M16BD / NT6DM16M32BC Version 1.4 20 Nanya Technology Corporation © 01/2016 All Rights Reserved 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) 11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes. 13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to VIL(AC) for falling input signals. 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 15. Input slew rate ≥ 1.0 V/ns. 16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns. 17. These parameters guarantee device timing but they are not necessarily tested on each device. 18. The transition time for address and command inputs is measured between VIH and VIL. 19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 24. Speed bin (CL - tRCD - tRP) = 3 - 3 - 3 25. Speed bin (CL - tRCD - tRP) = 3 - 4 - 4 (all speed bins except LPDDR200) 26. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms, if not already an integer, round to the next higher integer. 27. There must be at least two clock pulses during the tXSR period. 28. There must be at least one clock pulse during the tXP period. 29. tREFI values are dependent on density and bus width. 30. A maximum of 8 Refresh commands can be posted to any given LPDDR, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8*tREFI. 31. It’s not supported for package level. |
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