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NT5TU32M16FG-BE Datasheet(PDF) 32 Page - Nanya Technology Corporation. |
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NT5TU32M16FG-BE Datasheet(HTML) 32 Page - Nanya Technology Corporation. |
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32 / 107 page  32 Version 1.4 Nanya Technology Corp.© 12/2017 All Rights Reserved NTC Proprietary Level: Property DDR2 512Mb SDRAM NT5TU64M8FE / NT5TU32M16FG Seamless Burst Read Operation: RL = 5, AL = 2, CL = 3, BL = 4 NOP NOP NOP NOP NOP NOP NOP READ A Post CAS READ B Post CAS T0 T2 T1 T3 T4 T5 T6 T7 T8 Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2 Dout B3 RL = 5 AL = 2 CL = 3 SBR523 CMD DQ DQS, DQS CK, CK The seamle ss burst read operation’s supported by enabling a read command at every clock for BL=4 operation, and every 4 clock for BL=8 operation. This operation allows regardless of same or different banks as long as the banks activated. Burst Write Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1). A data strobe signal (DQS) has to be driven low (preamble) a time tWPRE prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is named “write recovery time” (WR). DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EM RS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timing measured is mode dependent. Basic Burst Write Timing DQS, DQS DQS DQS t DQSH tDQSL tWPRE WPST t Din Din Din Din t DS t DH |
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