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NT5TU32M16EG-AC Datasheet(PDF) 51 Page - Nanya Technology Corporation. |
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NT5TU32M16EG-AC Datasheet(HTML) 51 Page - Nanya Technology Corporation. |
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51 / 98 page  DDR2 512Mb SDRAM NT5TU64M8EE / NT5TU32M16EG 51 Version 1.6 Nanya Technology Corp.© 08/2015 All Rights Reserved Command Truth Table Function CKE CS RAS CAS WE BA0- BA1 A11- A13 A10 A0- A9 Notes Previous Cycle Current Cycle (Extended) Mode Register Set H H L L L L BA OP Code 1, 2 Auto-Refresh H H L L L H X X X X 1 Self-Refresh Entry H L L L L H X X X X 1,8 Self-Refresh Exit L H H X X X X X X X 1,7,8 L H H H Single Bank Precharge H H L L H L BA X L X 1,2 Precharge all Banks H H L L H L X X H X 1 Bank Activate H H L L H H BA Row Address 1,2 Write H H L H L L BA Column L Column 1,2,3 Write with Auto-Precharge H H L H L L BA Column H Column 1,2,3 Read H H L H L H BA Column L Column 1,2,3 Read with Auto-Precharge H H L H L H BA Column H Column 1,2,3 No Operation H X L H H H X X X X 1 Device Deselect H X H X X X X X X X 1 Power Down Entry H L H X X X X X X X 1,4 L H H H Power Down Exit L H H X X X X X X X 1,4 L H H H Notes: 1. All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock. 2. Bank addresses (BAx) determine which bank is to be operated upon. For (E) MRS BAx selects an (Extended) Mode Register. 3. Burst reads or writes at BL = 4 cannot be terminated. 4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh. 6. X means "H or L (but a defined logic level)". 7. Self refresh exit is asynchronous. 8. Vref must be maintained during Self Refresh operation. |
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