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NT5CC256M16ER-DIH Datasheet(PDF) 22 Page - Nanya Technology Corporation. |
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NT5CC256M16ER-DIH Datasheet(HTML) 22 Page - Nanya Technology Corporation. |
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22 / 154 page  Version 1.4 22 Nanya Technology Cooperation © 05/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 4Gb SDRAM NT5CB(C)512M8EQ/NT5CB(C)256M16ER Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The Mode Register 2 is written by asserting low on , RA, A, WE high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the table below. MR2 Definition BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 0 0 SRT ASR A6 0 1 A10 A9 0 0 0 1 1 0 1 1 A5 A4 A3 0 0 0 A7 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 BA1 BA0 1 1 1 0 0 0 1 1 0 1 1 MR select 0 Rtt_WR CWL PASR RFU CWL RFU 8 (1.5ns>=tCK(avg)>=1.25ns) 9 (1.25ns>=tCK(avg)>=1.07ns) RFU RFU RFU ASR Manual SR Reference (SRT) ASR enable Rtt_WR Dynamic ODT off RZQ/4 RZQ/2 Reserved RFU SRT MR1 MR2 MR3 Normal operating temperature range Extended operating temperature range 0 1 MR select MR0 * 1 : BA2, A5, A8, A11 ~ A15 are RFU and must be programmed to 0 during MRS. * 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available. |
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