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NT5CC256M16ER-EKH Datasheet(PDF) 41 Page - Nanya Technology Corporation. |
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NT5CC256M16ER-EKH Datasheet(HTML) 41 Page - Nanya Technology Corporation. |
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41 / 155 page  Version 1.3 41 Nanya Technology Cooperation © 03/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 4Gb SDRAM NT5CB(C)512M8EQ/NT5CB(C)256M16ER Timing details of Write leveling sequence (For Information. Only Support prime DQ) DQS - is capturing CK - low at T1 and CK - high at T2 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CMD ODT Di ff_ DQS Prime DQ Late Re ma ini ng DQs tMOD tWLMR D tWLO tWLS t WLH tWLOE tWLS t WLH t WLO NOP M RS tDQSH tDQSL tDQSH t DQSL T1 T2 Time break Do not Care On e Pri me DQ: Earl y Re ma ini ng DQs tWLO t WLO Undefined Driving Mode tWLOE tWLO t WLO All DQs are Prime : Late Re ma ini ng DQs Earl y Re ma ini ng DQs tWLMRD tWLO t WLO t WLOE tWLDQSEN NOP Note: 1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state through out the leveling procedure. 2. MRS: Load MR1 to enter write leveling mode 3. NOP: NOP or deselect 4. diff_DQS is the differential data strobe (DQS, ). Timing reference points are the zero crossings. DQS is shown with solid line, is shown with dotted line. 6. DQS/ needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. Write Leveling Mode Exit The following sequence describes how Write Leveling Mode should be exited: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0). 3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1). |
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