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CY28408 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part No. CY28408
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28408 Datasheet(HTML) 3 Page - Cypress Semiconductor

 
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CY28408
Document #: 38-07617 Rev. **
Page 3 of 19
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts block write and block
read operations from the controller. For block write/read
operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
8:2
Slave address – 7 bits
8:2
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 Bits
18:11
Command Code – 8 Bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
28
Acknowledge from slave
27:21
Slave address – 7 bits
36:29
Data byte 1 – 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
45:38
Data byte 2 – 8 bits
37:30
Byte Count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
....
Data Byte /Slave Acknowledges
46:39
Data byte 1 from slave – 8 bits
....
Data Byte N –8 bits
47
Acknowledge
....
Acknowledge from slave
55:48
Data byte 2 from slave – 8 bits
....
Stop
56
Acknowledge
....
Data bytes from slave / Acknowledge
....
Data Bte N from slave – 8 bits
....
NOT Acknowledge
...
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1Start
1Start
8:2
Slave address – 7 bits
8:2
Slave address – 7 bits
9Write
9Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits


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