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CY28408 Datasheet(PDF) 10 Page - Cypress Semiconductor

Part No. CY28408
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28408 Datasheet(HTML) 10 Page - Cypress Semiconductor

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CY28408
Document #: 38-07617 Rev. **
Page 10 of 19
PCI_STP# Assertion
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see
Figure 7). The PCI_F clocks will not be affected by this pin if
their control bits in the SMBus register are set to allow them to
be free running.
PCI_STP# – Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCI_F clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Note that the PCI STOP function is controlled by two inputs.
One is the device PCI_STP# pin number 34 and the other is
SMBus byte 0 bit 3. These two inputs to the function are
logically ANDed. If either the external pin or the internal
SMBus register bit is set low then the stoppable PCI clocks will
be stopped in a logic low state. Reading SMBus Byte 0 Bit 3
will return a 0 value if either of these control bits are set LOW
thereby indicating the devices stoppable PCI clocks are not
running.
PD# (Power-down) Clarification
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low ‘stopped’ state.
PD# – Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock, then on the next HIGH-to-LOW transition
of PCIF, the PCIF clock is stopped LOW. On the next
HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped
LOW. From this time, each clock will stop LOW on its next
HIGH-to-LOW transition, except the CPUT clock. The CPU
clocks are held with the CPUT clock pin driven HIGH with a
value of 2 x Iref, and CPUC undriven. After the last clock has
stopped, the rest of the generator will be shut down.
1
1
1
1
Running
Running
Running
Running
1
1
1
0
Hi Z
Hi Z
Running
Running
1
1
0
1
Hi ZHi ZHi Z
Hi Z
1
1
0
0
Hi ZHi ZHi Z
Hi Z
Table 9. Cypress Clock Power Management Truth Table (continued)
B0b6
B1b6
PD#
CPU_STP# Stoppable CPUT
Stoppable CPUC
Non-Stop CPUT Non-Stop CPUC
PCI_STP#
PCI_F
PCI
setup
t
Figure 5. PCI_STP# Assertion Waveform
PCI_STP#
PCI_F
PCI
setup
t
Figure 6. PCI_STP# Deassertion Waveform


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