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CY28408 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part No. CY28408
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28408 Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY28408
Document #: 38-07617 Rev. **
Page 7 of 19
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via
Byte8 and Byte9. See our App Note AN-0025 for details on our
Dial-a-Frequency feature.
P is a large value PLL constant that depends on the frequency
selection achieved through the hardware selectors (S1, S0).
P value may be determined from Table 6.
USB and DOT 48M Phase Relationship
The 48M_USB and 48M_DOT clocks are normally in phase. It
is understood that the difference in edge rate will introduce
some inherent offset. When 3V66_1/VCH clock is configured
for VCH (48-MHz) operation it is also in phase with the USB
and DOT outputs. See Figure 1.
Byte 7: Reserved
Bit
@Pup
Name
Description
70
Reserved
60
Reserved
50
Reserved
40
Reserved
31
Reserved
21
Reserved
11
Reserved
00
N8, MSB
Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional)
Bit
@Pup
Name
Description
70
N7
60
N6
50
N5
40
N4
30
N3
20
N2
10
N3
00
N0, LSB
Byte 9: Dial-a-Frequency™ Control Register R (all bits are read and write functional)
Bit
@Pup
Name
Description
70
R6 MSB
60
R5
50
R4
40
R3
30
R2
20
R1
10
R0, LSB
0
0
R and N register mux selection. 0 = R and N values come from the ROM.
1 = data is loaded from DAF (SMBus) registers.
Table 6. P Value
S(1:0)
P
0 0
32005333
0 1
48008000
1 0
96016000
1 1
64010667


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