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CY28408 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY28408
Description  Clock Synthesizer with Differential CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28408 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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CY28408
Document #: 38-07617 Rev. **
Page 4 of 19
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Data byte – 8 bits
20
Repeated start
28
Acknowledge from slave
27:21
Slave address – 7 bits
29
Stop
28
Read
29
Acknowledge from slave
37:30
Data from slave – 8 bits
38
NOT Acknowledge
39
Stop
Byte 0: CPU Clock Register[2]
Bit
@Pup
Name
Description
70
Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
60
CPU clock Power-down Mode Select. 0 = Drive CPUT to 4 or 6 IREF and
drive CPUC to low when PD# is asserted LOW. 1 = Three-state all CPU
outputs. This is only applicable when PD# is LOW. It is not applicable to
CPU_STP#.
5
0
3V66_1/VCH
3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
4
Pin 53
CPU_STP#
Reflects the current value of the external CPU_STP#. This bit is Read-only.
3
Pin 34
PCI_STP#
Reflects the current value of the internal PCI_STP# function when read.
Internally PCI_STP# is a logical AND function of the internal SMBus register
bit and the external PCI_STP# pin. This is a Read and Write control bit.
2
Pin 40
SEL2
Frequency Select Bit 2. Reflects the value of SEL2. This bit is Read-only.
1
Pin 55
SEL1
Frequency Select Bit 1. Reflects the value of SEL1. This bit is Read-only.
0
Pin 54
SEL0
Frequency Select Bit 0. Reflects the value of SEL0. This bit is Read-only.
Byte 1: CPU Clock Register
Bit
@Pup
Name
Description
7
Pin 43
MULT0 Value. This bit is Read-only.
60
Controls functionality of CPUT/C outputs when CPU_STP# is asserted. 0
= Drive CPUT to 4 or 6 IREF and drive CPUC to low when CPU_STP# is
asserted LOW. 1 = Tri-state all CPU outputs when CPU_STP# is
asserted.This bit will override Byte0, Bit6 such that even if it is a 0, when
PD# goes low the CPU outputs will be tri-stated.
50
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
40
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
30
Controls CPUT0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
2
1
CPUT/C2
CPUT/C2 Output Control
1 = enabled, 0 = three-state CPUT/C2
This is a Read and Write control bit.
Note:
2. PU = Internal Pull-up. PD = Internal Pull-down. T = Tri-level logic input.
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description


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