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ZL50018 Datasheet(PDF) 33 Page - Zarlink Semiconductor Inc

Part # ZL50018
Description  2 K Digital Switch with Enhanced Stratum 3 DPLL
Download  136 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

ZL50018 Datasheet(HTML) 33 Page - Zarlink Semiconductor Inc

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ZL50018
Data Sheet
33
Zarlink Semiconductor Inc.
7.5
External High Impedance Control Advancement
The external high impedance signals can be programmed to better match the timing required by the external
buffers. By default, the output timing of the STOHZ signals follows the programmed channel delay and bit offset of
their corresponding ST-BUS/GCI-Bus output streams. In addition, for all high impedance streams operating at any
data rate except 16.384 Mbps, the user can advance the STOHZ signals a further 0, 1/4, 1/2, 3/4 or 4/4 bits by
programming STOHZ[n]A 2 - 0 (bit 11 - 9) in the Stream Output Control Register. When the stream is operating at
16.384 Mbps, the additional STOHZ advancement can be set to 0, 1/2 or 4/4 bits by programming the same
register.
Figure 18 - Channel Switching External High Impedance Control Timing
8.0
Data Delay Through the Switching Paths
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform timeslot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications, select variable throughput delay to ensure minimum
delay between input and output data. In wideband data applications, select constant delay to maintain the frame
integrity of the information through the switch. The delay through the device varies according to the type of
throughput delay selected by the V/C (bit 14) in the Connection Memory Low when CMM = 0.
8.1
Variable Delay Mode
Variable delay mode causes the output channel to be transmitted as soon as possible. This is a useful mode for
voice applications where the minimum throughput delay is more important than frame integrity. The delay through
the switch can vary from 7 channels to 1 frame + 7 channels. To set the device into variable delay mode, VAREN
(bit 4) in the Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0.
If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the
output stream will not be valid.
In variable delay mode, the delay depends on the combination of the source and destination channels of the input
and output streams.
CH0
CH1
CH2
CH3
Last-2 Last-1 Last
CH0
Last
HiZ
FPi
STio[n]
STOHZ[n]
STOHZ[n]
(with Advancement)
(Default = No Advancement)
STOHZ Advancement (Programmable in 4 steps of 1/4 bit
for 2.048 Mbps, 4.096 Mbps and 8.192 Mbps
Programmable in 2 steps of 1/2 bit for 16.384 Mbps)
NOTE: n = 0 to 15
NOTE: Last = Last Channel of 31, 63, 127 and 255 for 2.048 Mbps, 4.096 Mbps. 8.192 Mbps and 16.384 Mbps modes respectively.
Output Frame Boundary


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