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ZL50018 Datasheet(PDF) 29 Page - Zarlink Semiconductor Inc |
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ZL50018 Datasheet(HTML) 29 Page - Zarlink Semiconductor Inc |
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29 / 136 page  ZL50018 Data Sheet 29 Zarlink Semiconductor Inc. 7.0 Data Input Delay and Data Output Advancement Various registers are provided to adjust the input delay and output advancement for each input and output data stream. The input bit delay and output bit advancement can vary from 0 to 7 bits for each individual stream. If input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. The sampling point can vary from 1/4 to 4/4 with a 1/4-bit increment for all input streams unless the stream is operating at 16.384 Mbps, in which case the fractional bit delay has a 1/2-bit increment. By default, the sampling point is set to the 3/4-bit location for non-16.384 Mbps data rates and the 1/2-bit location for the 16.384 Mbps data rate. The fractional output bit advancement can vary from 0 to 3/4 bits, again with a 1/4-bit increment unless the output stream is operating at 16.384 Mbps, in which case the output fractional bit advancement has a 1/2-bit increment from 0 to 1/2 bit. By default, there is 0 output bit advancement. Although input delay or output advancement features are available on streams which are operating in bi-directional mode it is not recommended, as it can easily cause bus contention. If users require this function, special attention must be given to the timing to ensure contention is minimized. 7.1 Input Bit Delay Programming The input bit delay programming feature provides users with the flexibility of handling different wire delays when designing with source streams for different devices. By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream Input Control Register 0 - 31 (SICR0 - 31) as described in Table 61 on page 93. The input bit delay can range from 0 to 7 bits. Figure 13 - Input Bit Delay Timing Diagram (ST-BUS) FPi STi[n] Bit Delay = 0 (Default) Channel 0 7 Channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 Channel 2 2 1 0 4 3 Last Channel STi[n] Bit Delay = 1 Channel 0 7 Channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 Channel 2 2 1 0 4 3 Last Channel Bit Delay = 1 5 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. |
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