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ZL50018 Datasheet(PDF) 80 Page - Zarlink Semiconductor Inc |
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ZL50018 Datasheet(HTML) 80 Page - Zarlink Semiconductor Inc |
80 / 136 page ZL50018 Data Sheet 80 Zarlink Semiconductor Inc. Bit Name Description 15 - 0 MNL15 - 0 Multiple-Period Near Lower Limit Bits: Total binary value of these bits and the MPNLLRU register bits defines the near lower limit for the multiple period count of any reference input, minus 1. The unit of the binary value is measured in 100 MHz clock periods. Note 1: The default value represents near lower limit for all reference frequencies, which is -9.913 ppm (Stratum 3 compliant value), regardless of the reference frequency. Note 2: The name ’lower’ is based on frequency. Table 46 - Multi-period Near Lower Limit Register - Lower 16 Bits (MPNLLRL) Bit Name Description 15 - 0 MNL31 - 16 Multiple-Period Near Lower Limit Bits: Total binary value of these bits and the MPNLLRL register bits defines the near lower limit for the multiple period count of any reference input, minus 1. The unit of the binary value is measured in 100 MHz clock periods. Note 1: The default value represents near lower limit for all reference frequencies, which is -9.913 ppm (Stratum 3 compliant value), regardless of the reference frequency. Note 2: The name ’lower’ is based on frequency. Table 47 - Multi-period Near Lower Limit Register - Upper 16 Bits (MPNLLRU) External Read/Write Address: 0052H Reset Value:F0B8H (Note 1) 15 14 13 12 11 10 9 8765 432 10 MNL 15 MNL 14 MNL 13 MNL 12 MNL 11 MNL 10 MNL 9 MNL 8 MNL 7 MNL 6 MNL 5 MNL 4 MNL 3 MNL 2 MNL 1 MNL 0 External Read/Write Address: 0053H Reset Value: 3B9AH (Note 1) 15 14 13 12 11 10 9 8765 432 10 MNL 31 MNL 30 MNL 29 MNL 28 MNL 27 MNL 26 MNL 25 MNL 24 MNL 23 MNL 22 MNL 21 MNL 20 MNL 19 MNL 18 MNL 17 MNL 16 |
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