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S75PL127JBF Datasheet(PDF) 46 Page - SPANSION

Part # S75PL127JBF
Description  Power supply woltage of 2.7 to 3.1 volt
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August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
47
Prel imin ary
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 13 shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read
mode and addresses are no longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write
Operation Status section for information on these status bits.
Any commands written during the chip erase operation are ignored. Note that
SecSi Sector, autoselect, and CFI functions are unavailable when a [program/
erase] operation is in progress. However, note that a hardware reset immedi-
ately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once that bank has returned to reading array data,
to ensure data integrity.
Note: See Table 13 for program command sequence.
Figure 4. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress


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