ISPPAC-CLK5520V-01TN100C datasheet(8/43 Pages) LATTICE

Part #	ISPPAC-CLK5520V-01TN100C

Description	In-System Programmable Clock Generator with Universal Fan-Out Buffer

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Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

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Lattice Semiconductor

ispClock5500 Family Data Sheet

8

Output Test Loads

Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other

selected parameters as noted in the various tables of this data sheet.

Figure 3. CMOS Termination Load

Figure 4. HSTL/SSTL Termination Load

Figure 5. LVDS/LVPECL Termination Load

50Ω

1kΩ

5pF

Test

Point

Z=50Ω

Equivalent

Termination Load

≈20Ω (HSTL)

40Ω (SSTL)

50Ω

5pF

Test

Point

Z=50Ω

Equivalent

Termination Load

VT=1.65 V (SSTL3)

1.25 V (SSTL2)

0.75 V (HSTL)

50Ω

+Test

Point

Equivalent

Termination Load

0.1µF

5pF

-Test

Point

5pF

Z=50Ω

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ISPPAC-CLK5520V-01TN100C Datasheet(PDF) 8 Page - Lattice Semiconductor

ISPPAC-CLK5520V-01TN100C Datasheet(HTML) 8 Page - Lattice Semiconductor

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