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DAC7811IDGSR Datasheet(PDF) 10 Page - Texas Instruments |
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DAC7811IDGSR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 18 page www.ti.com OPA277 DAC7811 I OUT1 V OUT 15V V+ V − −15V R FB GND V DD V DD V REF I OUT2 Serial Interface Input Shift Register DAC7811 SBAS337 – APRIL 2005 Theory of Operation (continued) For best linearity performance of the DAC7811, an op amp (OPA277) is recommended (see Figure 26). This circuit allows VREF swinging from –10 V to +10 V. Figure 26. Voltage Output Configuration Table 2. Control Logic Truth Table(1) CLK SYNC SERIAL SHIFT REGISTER DAC REGISTER X H No effect Latched ↑+ L Shift register data advanced one bit Latched X ↑+ In daisy-chain mode the function as determined by In daisy-chain mode the contents may chage C3-C0 is executed. as determined by C3-C0. (1) ↑+ Positive logic transition; X = Do not care. The DAC7811 has a three-wire serial interface (SYNC, SCLK, and SDIN), which is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most Digital Signal Processor (DSP) devices. See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the DAC7811 compatible with high-speed DSPs. The SDIN and SCLK input buffers are gated off while SYNC is high which minimizes the power dissipation of the digital interface. After SYNC goes low, the digital interface will respond to the SDIN and SCLK input signals and data can now be shifted into the device. If an inactive clock edge occurs after SYNC goes low, but before the first active clock edge, it will be ignored. If the SDO pin is being used then SYNC must remain low until after the inactive clock edge that follows the 16th active clock edge. The input shift register is 16 bits wide, as shown in Figure 27. The four MSBs are the control bits C3 – C0; these bits determine which function will be executed at the rising edge of SYNC in daisy-chain mode or the 16th active clock edge in stand-alone mode. The remaining 12 bits are the data bits. On a load and update command (C3–C0 = 0001) these 12 data bits will be transferred to the DAC register; otherwise, they have no effect. 4 CONTROL BITS 12 DATA BITS C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB DB15 Figure 27. Contents of the 16-Bit Input Shift Register 10 |
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