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SYNC Interrupt

Daisy-Chain

t

CSS

t

CH

t

DS

t

DH

t

DDS

t

CC

t

CST

t

9

t

C

SCLK

SYNC

SDIN

DB15

(N)

DB0

(N)

DB15

(N)

DB0

(N)

DB15

(N + 1)

DB0

(N + 1)

SDO

Control Bits C3 to C0

DAC7811

SBAS337 – APRIL 2005

In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is

updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an

interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an

update of the DAC register contents or a change in the operating mode occurs.

The DAC7811 powers up in the daisy chain mode which must be used when 2 or more devices are connected in

tandem. The SCLK and SYNC signals are shared across all devices while the SDO output of the first device

connects to the SDIN input of the following device, and so forth. In this configuration 16 SCLK cycles for each

DAC7811 in the chain are required. Please refer to the timing diagram of Figure 28.

For n devices in a daisy-chain configuration, 16n SCLK cycles are required to shift in the entire input data

stream. After 16n active SCLK edges are received following a falling SYNC, the data stream becomes complete,

and SYNC can brought high to update n devices simultaneously.

When SYNC is brought high, each device will execute the function defined by the four DAC control bits C3-C0 in

its input shift register. For example, C3-C0 must be 0001 for each DAC in the chain that is to be updated with

new data, and C3-C0 must be 0000 for each DAC in the chain whose contents are to remain unchanged.

A continuous stream containing the exact number of SCLK cycles may be sent first while the SYNC signal is held

low, and then raise SYNC at a later time. Nothing happens until the rising edge of SYNC, and then each

DAC7811 in the chain will execute the function defined by the four DAC control bits C3-C0 in its input shift

register.

Figure 28. DAC7811 Timing Diagram

Control Bits C3 to C0 allow control of various functions of the DAC; see Table 3. Default settings of the DAC on

powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled.

Device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow the

user to adjust certain features as part of an initialization sequence, for example, daisy-chaining may be disabled

if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero or

midscale. The user may also initiate a readback of the DAC register contents for verification purposes.

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