74HC139 datasheet(4/6 Pages) SS | High Speed CMOS Logic

Part #	74HC139

Description	High Speed CMOS Logic

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DC Electrical Characteristics (Voltages Referenced to GND)

High Speed CMOS Logic – 74HC139

Rev 1.0

16/04/18

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

1.9

4.5V

4.4

VIN = VIH or VIL

│IOUT│≤ 20µA

6.0V

5.9

4.5V

VIN = VIH or VIL

│IOUT│≤ 4.0mA

3.98

3.84

Minimum High-Level

Output Voltage

VOH

V

6.0V

VIN = VIH or VIL

│IOUT│≤ 5.2mA

5.48

5.34

2.0V

0.1

4.5V

0.1

6.0V

VIN = VIH or VIL

│IOUT│≤ 20µA

0.1

4.5V

VIN = VIH or VIL

│IOUT│≤ 4.0mA

0.26

0.33

Maximum Low-Level

Output Voltage

VOL

6.0V

VIN = VIH or VIL

│IOUT│≤ 5.2mA

0.26

0.33

V

Maximum Input

Leakage Current

IIN

6.0V

VIN = VCC or GND

±0.1

±1.0

µA

Maximum Quiescent

Supply Current

ICC

6.0V

VIN = VCC or GND

IOUT = 0µA

4

40

µA

AC Electrical Characteristics5

LIMITS

PARAMETER

6. Not production tested in die form, characterized by chip design and tested in package.

7. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

SYMBOL

VCC

CONDITIONS

UNITS

FULL RANGE

4

25°C

85°C

2.0V

115

145

4.5V

23

29

Maximum

Propagation Delay,

CL = 50pF,

ns

tPLH, tPHL

Select to Output Y

tr = tf = 6ns

(Figure 1, 3)

6.0V

20

25

2.0V

115

145

4.5V

23

29

Maximum

Propagation Delay,

CL = 50pF,

ns

tPLH, tPHL

Input A to Output Y

tr = tf = 6ns

(Figure 2,3)

6.0V

20

25

2.0V

75

95

4.5V

15

19

Maximum Output

Transition Time,

CL = 50pF,

ns

tTLH, tTHL

Any Output

tr = tf = 6ns

(Figure 1,3)

6.0V

13

16

Maximum Input

Capacitance

CIN

-

10

pF

TYPICAL

Power Dissipation

TJ = 25°C,

Capacitance

(Per Decoder)

7

CPD

-

VCC = 5.0V

55

pF

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