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M50FLW080A Datasheet(PDF) 18 Page - STMicroelectronics |
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M50FLW080A Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 64 page  Bus operations M50FLW080A, M50FLW080B 18/64 3.1.2 Bus Write Bus Write operations are used to write to the Command Interface or Firmware Hub/Low Pin Count Registers. A valid Bus Write operation starts on the rising edge of the Clock signal when Input Communication Frame, FWH4/LFRAME, is Low, VIL, and the correct Start cycle is present on FWH0/LAD0-FWH3/LAD3. On subsequent Clock cycles the Host will send to the memory: ● ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-FWH3 in FWH mode. ● Cycle Type + Dir, Address, other control bits, Data0-Data3 and Data4-Data7 on LAD0- LAD3. The device responds by outputting Sync data until the wait states have elapsed. See Table 7 and Table 9, and Figure 7 and Figure 9, for a description of the Field definitions for each clock cycle of the transfer. See Table 26, and Figure 14, for details on the timings of the signals. 3.1.3 Bus Abort The Bus Abort operation can be used to abort the current bus operation immediately. A Bus Abort occurs when FWH4/LFRAME is driven Low, VIL, during the bus operation. The device puts the Input/Output Communication pins, FWH0/LAD0-FWH3/LAD3, to high impedance. Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received. A Bus Abort during the final TAR cycles is not guaranteed to abort the command. The bus, however, will be released immediately. 3.1.4 Standby When FWH4/LFRAME is High, VIH, the device is put into Standby mode, where FWH0/LAD0-FWH3/LAD3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. 3.1.5 Reset During the Reset mode, all internal circuits are switched off, the device is deselected, and the outputs are put to high-impedance. The device is in the Reset mode when Interface Reset, RP, or CPU Reset, INIT, is driven Low, VIL. RP or INIT must be held Low, VIL, for tPLPH. The memory reverts to the Read mode upon return from the Reset mode, and the Lock Registers return to their default states regardless of their states before Reset. If RP or INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the affected memory cells no longer contain valid data. The device can take up to tPLRH to abort a Program or Erase operation. 3.1.6 Block Protection Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. |
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