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M30L0R7000B0 Datasheet(PDF) 22 Page - STMicroelectronics

Part # M30L0R7000B0
Description  128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst), 1.8V Supply Flash Memory
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M30L0R7000B0 Datasheet(HTML) 22 Page - STMicroelectronics

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M30L0R7000T0, M30L0R7000B0
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STATUS REGISTER
The Status Register provides information on the
current or previous program or erase operations.
Issue a Read Status Register command to read
the contents of the Status Register, refer to Read
Status Register Command section for more de-
tails. To output the contents, the Status Register is
latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be
read until Chip Enable or Output Enable returns to
VIH. The Status Register can only be read using
single Asynchronous or Single Synchronous
reads. Bus Read operations from any address
within the bank, always read the Status Register
during program and erase operations.
The various bits convey information about the sta-
tus and any errors of the operation. Bits SR7, SR6,
SR2 and SR0 give information on the status of the
device and are set and reset by the device. Bits
SR5, SR4, SR3 and SR1 give information on er-
rors, they are set by the device but must be reset
by issuing a Clear Status Register command or a
hardware reset. If an error bit is set to ‘1’ the Status
Register should be reset before issuing another
command.
The bits in the Status Register are summarized in
Table 9., Status Register Bits. Refer to Table 9. in
conjunction with the following text descriptions.
Program/Erase Controller Status Bit (SR7). The
Program/Erase Controller Status bit indicates
whether the Program/Erase Controller is active or
inactive in any bank.
When the Program/Erase Controller Status bit is
Low (set to ‘0’), the Program/Erase Controller is
active; when the bit is High (set to ‘1’), the Pro-
gram/Erase Controller is inactive, and the device
is ready to process a new command.
The Program/Erase Controller Status bit is Low
immediately after a Program/Erase Suspend com-
mand is issued until the Program/Erase Controller
pauses. After the Program/Erase Controller paus-
es the bit is High.
Erase Suspend Status Bit (SR6). The
Erase
Suspend Status bit indicates that an erase opera-
tion has been suspended in the addressed block.
When the Erase Suspend Status bit is High (set to
‘1’), a Program/Erase Suspend command has
been issued and the memory is waiting for a Pro-
gram/Erase Resume command.
The Erase Suspend Status bit should only be con-
sidered valid when the Program/Erase Controller
Status bit is High (Program/Erase Controller inac-
tive). SR6 is set within the Erase Suspend Latency
time of the Program/Erase Suspend command be-
ing issued therefore the memory may still com-
plete the operation rather than entering the
Suspend mode.
When a Program/Erase Resume command is is-
sued the Erase Suspend Status bit returns Low.
Erase Status Bit (SR5). The Erase Status bit is
used to identify if there was an error during a block
or bank erase operation. When the Erase Status
bit is High (set to ‘1’), the Program/Erase Control-
ler has applied the maximum number of pulses to
the block or bank and still failed to verify that it has
erased correctly.
The Erase Status bit should be read once the Pro-
gram/Erase Controller Status bit is High (Program/
Erase Controller inactive).
Once set High, the Erase Status bit must be set
Low by a Clear Status Register command or a
hardware reset before a new erase command is is-
sued, otherwise the new command will appear to
fail.
Program Status Bit (SR4). The Program Status
bit is used to identify if there was an error during a
program operation.
The Program Status bit should be read once the
Program/Erase Controller Status bit is High (Pro-
gram/Erase Controller inactive).
When the Program Status bit is High (set to ‘1’),
the Program/Erase Controller has applied the
maximum number of pulses to the Word and still
failed to verify that it has programmed correctly.
Attempting to program a '1' to an already pro-
grammed bit while VPP = VPPH will also set the
Program Status bit High. If VPP is different from
VPPH, SR4 remains Low (set to '0') and the attempt
is not shown.
Once set High, the Program Status bit must be set
Low by a Clear Status Register command or a
hardware reset before a new program command is
issued, otherwise the new command will appear to
fail.
VPP Status Bit (SR3). The VPP Status bit is used
to identify an invalid voltage on the VPP pin during
program and erase operations. The VPP pin is only
sampled at the beginning of a program or erase
operation. Program and erase operations are not
guaranteed if VPP becomes invalid during an oper-
ation.
When the VPP Status bit is Low (set to ‘0’), the volt-
age on the VPP pin was sampled at a valid voltage.
when the VPP Status bit is High (set to ‘1’), the VPP
pin has a voltage that is below the VPP Lockout
Voltage, VPPLK, the memory is protected and pro-
gram and erase operations cannot be performed.
Once set High, the VPP Status bit must be set Low
by a Clear Status Register command or a hard-
ware reset before a new program or erase com-
mand is issued, otherwise the new command will
appear to fail.


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