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PALCE16V8 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part No. PALCE16V8
Description  Flash-Erasable Reprogrammable CMOS PAL Device
Download  13 Pages
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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PALCE16V8 Datasheet(HTML) 6 Page - Cypress Semiconductor

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USE ULTRA37000™ FOR
ALL NEW DESIGNS
PALCE16V8
Document #: 38-03025 Rev. *A
Page 6 of 13
tWH
Clock Width HIGH[7]
3
46
8
12
ns
tWL
Clock Width LOW[7]
3
46
8
12
ns
fMAX1
External Maximum
Frequency (1/(tCO + tS))
[7, 11]
143
100
69
45.5
37
MHz
fMAX2
Data Path Maximum
Frequency (1/(tWH + tWL))
[7, 12]
166
125
83
62.5
41.6
MHz
fMAX3
Internal Feedback
Maximum Frequency
(1/(tCF + tS))
[7, 13]
166
125
74
50
40
MHz
tCF
Register Clock to
Feedback Input[7, 14]
3
3
6
8
10
ns
tPR
Power-Up Reset Time[7]
1
11
1
1
µs
Commercial and Industrial Switching Characteristics (continued)[2]
Parameter
Description
16V8-5
16V8-7
16V8-10
16V8-15
16V8-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Military Switching Characteristics[7]
16V8-10
16V8-15
16V8-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
Propagation Delay[8, 9]
310
3
15
3
25
ns
tPZX
OE to Output Enable
10
15
20
ns
tPXZ
OE to Output Disable
10
15
20
ns
tEA
Input to Output Enable Delay[7]
10
15
25
ns
tER
Input to Output Disable Delay[7, 10]
10
15
25
ns
tCO
Clock to Output Delay[8, 9]
272
10
2
12
ns
tS
Input or Feedback Set-up Time
10
12
15
ns
tH
Input Hold Time
.5
.5
.5
ns
tP
External Clock Period (tCO + tS)17
22
27
ns
tWH
Clock Width HIGH[7]
68
12
ns
tWL
Clock Width LOW[7]
68
12
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS)
[7, 11]
58
45.5
37
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))
[7, 12]
83
62.5
41.6
MHz
fMAX3
Internal Feedback Maximum
Frequency (1/(tCF + tS))
[7, 13]
62.5
50
40
MHz
tCF
Register Clock to
Feedback Input[7, 14]
68
10
ns
tPR
Power-Up Reset Time[7]
11
1
µs


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