SN65LVDS151

MuxIt

™ SERIALIZER-TRANSMITTER

SLLS444A – DECEMBER 2000

2

POST OFFICE BOX 655303

description (continued)

Data is parallel loaded into the SN65LVDS151 input latches on the first rising edge of the M-clock input (MCI)

signal following a rising edge of the link clock reference input (LCRI). The data is read out serially from the

SN65LVDS151 shift registers on the rising edges of the M-clock input (MCI). The lowest order bit of parallel input

data, DI – 0, is output from DO on the third rising edge of MCI following the rising edge of LCRI. The remaining

bits of parallel input data, DI-1

→ DI-(M-1) are clocked out sequentially, in ascending order, by subsequent MCI

rising edges. The link clock output (LCO) signal rising edge is synchronized to the data output (DO) by an internal

circuit clocked by MCI. The LCO signal rising edge follows the first rising edge of MCI after the rising edge of

LCRI. Examples of operating waveforms for values of M = 4 and M = 10 are provided in Figure 1.

Both the LCRI and MCI signals are intended to be sourced from the SN65LVDS150 MuxIt programmable

frequency multiplier. They are carried over LVDS differential connections to minimize skew and jitter. The

SN65LVDS151 includes LVDS differential line drivers for both the serialized data output (DO) stream and the

link clock output (LCO). The cascade input (CI) is also an LVDS connection, and when it is used it is tied to the

DO output of the preceding SN65LVDS151.

An internal power-on reset (POR) and an enable input (EN) control the operation of the SN65LVDS151. When

two differential outputs are enabled and operating to specifications. The link clock output enable input

(LCO_EN) is used to turn off the LCO output when it is not being used. Cascade input enable (CI_EN) is used

to turn off the CI input when it is not being used.

Serialized data bits are output from the DO output, starting in ascending order, from parallel input bit DI – 0. The

number of serialized data bits output per data clock cycle is determined by the multiplexing ratio M. For values

of M less than or equal to 10, the cascade input (CI

±) is not used, and only the first M parallel input bits (DI–0

thought DI – [M – 1]) are used. For values of M greater than 10, all ten parallel input bits (DI – 0 though DI – 9) are

used, and the cascade input is used to shift in the remaining data bits from additional SN65LVDS151 serializers.

Table 2 shows which input data bits are used as a function of the multiplier M.

Table 1. Example Combinations of LCRI and MCI Supported by the

SN65LVDS150 MuxIt Programmable PLL Frequency Multiplier

LCRI, MHz

MCI, MHz

M

MINIMUM

MAXIMUM

MINIMUM

MAXIMUM

4

5

50

20

200

10

5

20

50

200

20

5

10

100

200

40

5

5

200

200