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ISO7721BDW Datasheet(PDF) 17 Page - Texas Instruments

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Part No. ISO7721BDW
Description  High-Speed, Robust EMC, Basic Insulation Dual-Channel Digital Isolator
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

ISO7721BDW Datasheet(HTML) 17 Page - Texas Instruments

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Output
985
1.5 M
INx
VCCI
VCCI
VCCI
Input (Devices without F suffix)
985
1.5 M
INx
VCCI
VCCI
VCCI
VCCI
Input (Devices with F suffix)
VCCO
~20
OUTx
Copyright © 2016, Texas Instruments Incorporated
17
ISO7721B
www.ti.com
SLLSEY9A – APRIL 2018 – REVISED APRIL 2019
Product Folder Links: ISO7721B
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Copyright © 2018–2019, Texas Instruments Incorporated
(1)
VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered up (VCC ≥ 2.25 V); PD = Powered down (VCC ≤ 1.7 V); X = Irrelevant; H
= High level; L = Low level
(2)
A strongly driven input signal can weakly power the floating VCC via an internal protection diode and cause undetermined output.
(3)
The outputs are in undetermined state when 1.7 V < VCCI, VCCO < 2.25 V.
8.4 Device Functional Modes
Table 2 lists the functional modes for the ISO7721B device.
Table 2. Function Table(1)
VCCI
VCCO
INPUT
(INx)(2)
OUTPUT
(OUTx)
COMMENTS
PU
PU
H
H
Normal Operation:
A channel output assumes the logic state of the input.
L
L
Open
Default
Default mode: When INx is open, the corresponding channel output goes to the
default high logic state. The default is High for ISO7721B and Low for
ISO7721B with F suffix.
PD
PU
X
Default
Default mode: When VCCI is unpowered, a channel output assumes the logic
state based on the selected default option. The default is High for ISO7721B
and Low for ISO7721B with F suffix.
When VCCI transitions from unpowered to powered-up, a channel output
assumes the logic state of the input.
When VCCI transitions from powered-up to unpowered, channel output assumes
the selected default state.
X
PD
X
Undetermined
When VCCO is unpowered, a channel output is undetermined
(3).
When VCCO transitions from unpowered to powered-up, a channel output
assumes the logic state of the input
8.4.1 Device I/O Schematics
Figure 14. Device I/O Schematics


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