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CY28409 Datasheet(PDF) 7 Page - Cypress Semiconductor

Part No. CY28409
Description  Clock Synthesizer with Differential SRC and CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28409 Datasheet(HTML) 7 Page - Cypress Semiconductor

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CY28409
Document #: 38-07445 Rev. *B
Page 7 of 18
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28409 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, Set = 0
6
0
Reserved
Reserved, Set = 0
5
0
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRC Frequency Select
0 = 100Mhz, 1 = 200MHz
30
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Mode
0 = down (default), 1 = center
20
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision ID Bit 3
Revision ID Bit 3
6
1
Revision ID Bit 2
Revision ID Bit 2
5
0
Revision ID Bit 1
Revision ID Bit 1
4
0
Revision ID Bit 0
Revision ID Bit 0
3
1
Vendor ID Bit 3
Vendor ID Bit 3
2
0
Vendor ID Bit 2
Vendor ID Bit 2
1
0
Vendor ID Bit 1
Vendor ID Bit 1
0
0
Vendor ID Bit 0
Vendor ID Bit 0
Table 6. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm


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