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CY28409 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part No. CY28409
Description  Clock Synthesizer with Differential SRC and CPU Outputs
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Maker  CYPRESS [Cypress Semiconductor]
Homepage  http://www.cypress.com
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CY28409 Datasheet(HTML) 4 Page - Cypress Semiconductor

 
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CY28409
Document #: 38-07445 Rev. *B
Page 4 of 18
Control Registers
20:27
Byte Count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 1 – 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 2 – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge from master
....
......................
39:46
Data byte from slave – 8 bits
....
Data Byte (N–1) –8 bits
47
Acknowledge from master
....
Acknowledge from slave
48:55
Data byte from slave – 8 bits
....
Data Byte N –8 bits
56
Acknowledge from master
....
Acknowledge from slave
....
Data byte N from slave – 8 bits
....
Stop
....
Acknowledge from master
....
Stop
Table 4. Block Read and Block Write Protocol(continued)
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
Table 5. Byte Read and Byte Write protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1Start
1Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of the
command code represents the offset of the byte to
be accessed
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of
the command code represents the offset of the
byte to be accessed
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Data byte from master – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29
Stop
28
Read = 1
29
Acknowledge from slave
30:37
Data byte from slave – 8 bits
38
Acknowledge from master
39
Stop
Byte 0:Control Register 0
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, Set = 0
6
1
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
5
0
Reserved
Reserved, Set = 0
4
0
Reserved
Reserved, Set = 0


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