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XR16C854IQ Datasheet(PDF) 4 Page - Exar Corporation |
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XR16C854IQ Datasheet(HTML) 4 Page - Exar Corporation |
4 / 54 page XR16C854/854D áç áç áç áç 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO REV. 3.0 4 PIN DESCRIPTIONS Pin Description NAME 64-TQFP PIN # 68-PLCC PIN# 100-QFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 22 23 24 32 33 34 37 38 39 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A-D during a data bus transac- tion. D7 D6 D5 D4 D3 D2 D1 D0 60 59 58 57 56 55 54 53 5 4 3 2 1 68 67 66 95 94 93 92 91 90 89 88 I/O Data bus lines [7:0] (bidirectional). IOR# (N.C.) 40 52 66 I When 16/68# pin is at logic 1, the Intel bus interface is selected and this input becomes read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input is not used. IOW# (R/W#) 9 18 15 I When 16/68# pin is at logic 1, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal. Motorola bus interface is not available on the 64 pin pack- age. CSA# (CS#) 7 16 13 I When 16/68# pin is at logic 1, this input is chip select A (active low) to enable channel A in the device. When 16/68# pin is at logic 0, this input becomes the chip select (active low) for the Motorola bus interface. Motorola bus interface is not available on the 64 pin package. CSB# (A3) 11 20 17 I When 16/68# pin is at logic 1, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is at logic 0, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Motorola bus interface is not available on the 64 pin package. CSC# (A4) 38 50 64 I When 16/68# pin is at logic 1, this input is chip select C (active low) to enable channel C in the device. When 16/68# pin is at logic 0, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. Motorola bus interface is not available on the 64 pin package. |
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