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TMS28F400BZB80BDBJE Datasheet(PDF) 10 Page - Texas Instruments |
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TMS28F400BZB80BDBJE Datasheet(HTML) 10 Page - Texas Instruments |
10 / 29 page TMS28F400BZT, TMS28F400BZB 524288 BY 8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SMJS400E – JUNE 1994 – REVISED JANUARY 1998 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 normal programming There are two CSM commands for programming: program setup and alternate program setup (see Table 1 ). After the desired command code is entered, the WSM takes over and correctly sequences the device to complete the program operation. During this time, the CSM responds only to status reads until the program operation has been completed, after which all commands to the CSM become valid again. Once a program command has been issued, the WSM cannot normally be interrupted until the program algorithm has been completed (see Figure 3 and Figure 4). Taking RP to VIL during programming aborts the program operation. During programming, VPP must remain at VPPH. Only 0s are written and compared during a program operation. If 1s are programmed, the memory cell contents do not change and no error occurs. A program-setup command can be aborted by writing FFh ( in byte-wide mode) or FFFFh ( in word-wide mode) during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads. When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated, all commands to the CSM become valid again. erase operations There are two erase operations that can be performed by the TMS28F400BZx devices: block erase and erase suspend / erase resume. An erase operation must be used to initialize all bits in an array block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend commands until the WSM completes its task. D Block erasure Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is accomplished only by blocks; data at single address locations within the array cannot be individually erased. The block to be erased is selected by using any valid address within that block. RP must be at VHH for changing the data content of the boot block. Block erasure is initiated by a command sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A two-command erase sequence protects against accidental erasure of memory contents. Erase setup and confirm commands are latched on the rising edge of E or W, whichever occurs first. Block addresses are latched during the block-erase-confirm command on the rising edge of E or W (see Figure 10 and Figure 11 ). When the block-erase-confirm command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is performed to ensure that all bits are correctly erased. Monitoring of the erase operation is possible through the status register (see the subsection, “read status register”). D Erase suspend/erase resume During the execution of an erase operation, the erase-suspend command (B0h ) can be entered to direct the WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the read-array, read-status-register, and erase-resume commands. During the erase-suspend operation, array data should be read from a block other than the one being erased. To resume the erase operation, an erase-resume command (D0h ) must be issued to cause the CSM to clear the suspend state previously set (see Figure 5 and Figure 6). automatic power-saving mode Substantial power savings are realized during periods when the array is not being read. During this time, the device switches to the automatic power-saving (APS) mode. When the device switches to this mode, ICC is typically reduced from 40 mA to 1 mA (IOUT = 0 mA). The low level of power is maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last memory-address read until a new address is read. This mode is entered automatically if no address or control pins toggle within a 200-ns time-out period. At least one transition on E must occur after power up to activate this mode. |
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