Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

TMS28F400BZB80BDBJE Datasheet(PDF) 9 Page - Texas Instruments

Part # TMS28F400BZB80BDBJE
Description  8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES
Download  29 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS28F400BZB80BDBJE Datasheet(HTML) 9 Page - Texas Instruments

Back Button TMS28F400BZB80BDBJE Datasheet HTML 5Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 6Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 7Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 8Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 9Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 10Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 11Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 12Page - Texas Instruments TMS28F400BZB80BDBJE Datasheet HTML 13Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 29 page
background image
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
command state machine operations (continued)
During an erase cycle, the CSM responds to status read and the erase-suspend commands. When the WSM
has completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when VPP is within its correct voltage range
(VPPH). For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the VPP status bit (SB3), the program status bit (SB4) and the erase status
bit (SB5) of the status register. The clear status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize internal operations. When the status bits are cleared, the device returns
to the read array mode.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D Read array
The array is read by entering the command code FFh on DQ0 – DQ7. Control pins E and G must be at a
logic-low level ( VIL) and W and RP must be at a logic-low level (VIH) to read data from the array. Data is
available on DQ0 – DQ15 (word-wide mode) or DQ0 – DQ7 (byte-wide mode ). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
D Read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0 – DQ7. Two bus cycles are
required for this operation. The first bus cycle is used to enter the command code and the second bus cycle
is used to read the device-equivalent code. Control pins E and G must be at a logic-low level ( VIL) and W and
RP must be at a logic-high level ( VIH). Two identifier bytes are accessed by toggling A0. The
manufacturer-equivalent code is obtained on DQ0 – DQ7 with A0 at a logic-low level ( VIL). The
device-equivalent code is obtained when A0 is set to a logic-low level ( VIH). Alternatively, the manufacturer-
and device-equivalent codes can be read by applying VID (nominally 12 V) to A9 and selecting the desired
code by toggling A0 high or low. All other addresses are in the “don’t care” category (see Table 2, Table 4,
and Table 5).
D Read status register
The status register is read by entering the command code 70h on DQ0 – DQ7. Control pins E and G must be
at a logic-low level ( VIL) and W and RP must be at a logic-low level (VIH). Two bus cycles are required for this
operation: one to enter the command code and a second to read the status register. In a given read cycle, the
status-register contents are updated on the falling edge of E or G, whichever occurs last within the cycle.
boot-block programming / erasing
Should changes to the boot block be required, RP must be set to VHH (12 V) and VPP must be set to the
programming voltage level ( VPPH). If an attempt is made to write, erase or erase-suspend the boot block without
RP at VHH, an error signal is generated on SB4 (program-status bit) or SB5 (erase-status bit).
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to status
reads. When the WSM status bit (SB7) is set to a logic-low level, signifying termination of the nonprogram
operation, all commands to the CSM become valid again.


Similar Part No. - TMS28F400BZB80BDBJE

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
TMS28F400BZB TI1-TMS28F400BZB Datasheet
409Kb / 29P
[Old version datasheet]   BOOT-BLOCK FLASH MEMORIES
More results

Similar Description - TMS28F400BZB80BDBJE

ManufacturerPart #DatasheetDescription
logo
Texas Instruments
TMS28F200BZT TI-TMS28F200BZT Datasheet
405Kb / 29P
[Old version datasheet]   262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES
TMS28F002AXY TI-TMS28F002AXY Datasheet
1Mb / 79P
[Old version datasheet]   262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
TMS28F004AXY TI-TMS28F004AXY Datasheet
1Mb / 80P
[Old version datasheet]   524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
TMS28F004AEB TI1-TMS28F004AEB Datasheet
1Mb / 80P
[Old version datasheet]   524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
TMS29F400B TI-TMS29F400B Datasheet
670Kb / 51P
[Old version datasheet]   524288 BY 8-BIT/262144 BY 16-BIT FLASH MEMORIES
TMS29F002B TI1-TMS29F002B Datasheet
453Kb / 38P
[Old version datasheet]   262144 BY 8-BIT FLASH MEMORIES
TMS29F002RB TI1-TMS29F002RB Datasheet
517Kb / 41P
[Old version datasheet]   262144 BY 8-BIT FLASH MEMORIES
TMS28F008AEB TI1-TMS28F008AEB Datasheet
696Kb / 52P
[Old version datasheet]   1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
TMS28F008AXY TI-TMS28F008AXY Datasheet
714Kb / 52P
[Old version datasheet]   1 048 576 BY 8-BIT/524 288 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
TMS29F800T TI-TMS29F800T Datasheet
685Kb / 51P
[Old version datasheet]   1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com