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XR16C854IJ Datasheet(PDF) 1 Page - Exar Corporation |
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XR16C854IJ Datasheet(HTML) 1 Page - Exar Corporation |
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1 / 54 page  Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç áç áç áç XR16C854/854D 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO JANUARY 2004 REV. 3.0 GENERAL DESCRIPTION The XR16C854/854D1 (854) is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 128 bytes of transmit and receive FIFOs, transmit and receive FIFO counters and trigger levels, automatic hardware and software flow control, and data rates of up to 2 Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver error indications, and modem serial interface controls. System interrupts may be tailored to meet design requirements. An internal loopback capability allows onboard diagnostics. The 854 is available in 64-pin TQFP, 68-pin PLCC and 100-pin QFP packages. The 64-pin package only offers the 16 mode interface, but the 68 and 100 pin packages offer an additional 68 mode interface which allows easy integration with Motorola processors. The XR16C854CV (64 pin) offers three state interrupt outputs while the XR16C854DV provides continuous interrupt outputs. The 100 pin package provides additional FIFO status outputs (TXRDY# and RXRDY# A-D), separate infrared transmit data outputs (IRTX A-D) and channel C external clock input (CHCCLK). The XR16C854/854D is compatible with the industry standard ST16C554/554D and ST16C654/654D. NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787. FEATURES Added feature in devices with top mark date code of "F2 YYWW" and newer: s 5 volt tolerant inputs • 2.97 to 5.5 Volt Operation • Pin-to-pin compatible with the industry standard ST16C554 and ST16C654 and TI’s TL16C554N and TL16C754BFN • Intel or Motorola Data Bus Interface select • Four independent UART channels s Register Set Compatible to 16C550 s Data rates of up to 2 Mbps s Transmit and Receive FIFOs of 128 bytes s Programmable TX and RX FIFO Trigger Levels s Transmit and Receive FIFO Level Counters s Automatic Hardware (RTS/CTS) Flow Control s Selectable Auto RTS Flow Control Hysteresis s Automatic Software (Xon/Xoff) Flow Control s Wireless Infrared (IrDA 1.0) Encoder/Decoder • Sleep Mode (200 uA typical) • Crystal oscillator or external clock input APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. XR16C854 BLOCK DIAGRAM XTAL1 XTAL2 Crystal Osc/Buffer Data Bus Interface UART Channel A 128 Byte TX FIFO 128 Byte RX FIFO BRG IR ENDEC TX & RX UART Regs 2.97V to 5.5V V CC GND 854 BLK TXB, RXB, IRTXB , DTRB#, DSRB#, RTSB#, CTSB #, CDB#, RIB#, OP2B# UART Channel B (sam e as Channel A ) A2:A0 D7:D0 CSA# 16/68# CSB# INTA INTB IOW # IOR# Reset INTSEL CHCCLK TXRDY# A-D RXRDY# A-D UART Channel C (sam e as Channel A ) TXA, RXA, IRTXA , DTRA#, DSRA#, RTSA#, CTSA #, CDA#, RIA#, OP2A# TXC, RX C, IR TXC, DTRC #, DSRC#, RTSC#, CTSC#, CDC#, RIC#, OP 2C# UART Channel D (sam e as Channel A ) TXD, RX D, IRTXD, DTRD#, DSRD#, RTSD#, CTSD#, CDD#, RID#, OP 2D# CSC# CSD# INTC INTD |
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