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TMS28F400BZT Datasheet(PDF) 5 Page - Texas Instruments

Part No. TMS28F400BZT
Description  8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS28F400BZT Datasheet(HTML) 5 Page - Texas Instruments

 
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TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. To
protect data within this memory sector, the RP pin can be used to provide a lockout to eliminate either accidental
erase or program operations. When RP is operated with normal TTL / CMOS logic levels, the contents of the
boot block cannot be erased or reprogrammed. Changes to the contents of the boot block can be made only
when RP is at VHH (nominally 12 V) during normal write/erase operations.
parameter block
Two parameter blocks of 8K bytes each can be used as a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution should be exercised because the parameter block does not
have the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F400BZx is located in four main blocks. Three of the blocks have storage
capacity for 128K bytes and the fourth block has storage capacity for 96K bytes.
command state machine
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. The available commands are listed in Table 1 and
the description of these commands are shown in Table 2. When a program or erase command is issued to the
CSM, the WSM controls the internal sequences and the CSM only responds to status reads. After the WSM
completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the CSM to respond to the
full command set again.
operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0 – DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires a command code to be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0 – DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
Table 1. Command State Machine Codes for Device Mode Selection
COMMAND
CODE ON
DQ0 – DQ7†
DEVICE MODE
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
Invalid / Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
† DQ0 is the least significant bit. DQ8 – DQ15 can be any valid 2-state
level.


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