s MSM7712 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

16

Oki Semiconductor

AC Characteristics

Processor Interface

The MSM7712 is designed to operate with the V80C86, V33, V53A, and 80C186 processors. Refer to the

appropriate processor data sheets for detailed information.

Host Interface

The MSM7712 meets the timing requirements of the PCMCIA interface. Wait states are used to provide

the access times to the shared RAM when required.

Shared Memory Interface

The shared memory cycle time is 2 RCK clock periods. When the memory interface is not active the data

bus RD[15:0] is output (low). This ensures the shared memory data bus does not float and consume

power.

1.

RCK at 16 MHz.

Parameter

Description

Min.

Typ.

Max.

Unit

Setup time of address, WR strobe and data output to RCE asserted

20

-

-

ns

Hold time of address, WR strobe and data output to RCE deasserted

10

-

-

RCE low period (with 16/32 MHz SCK)

85

-

-

Setup time of read data to RCE deasserted

10

-

-

RAM access time Tce -Ts (d-rce)

75

-

-

Hold time of read data to RCE deasserted

0

-

-

Hold time before data bus driven low

50

-

70

Figure 6. Shared Memory Timing

RA[], RWRN

RCEHN, RCELN

RD[], READ

RD[], WRITE