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MSM7712 Datasheet(PDF) 16 Page - OKI electronic componets |
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MSM7712 Datasheet(HTML) 16 Page - OKI electronic componets |
16 / 20 page s MSM7712 s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– 16 Oki Semiconductor AC Characteristics Processor Interface The MSM7712 is designed to operate with the V80C86, V33, V53A, and 80C186 processors. Refer to the appropriate processor data sheets for detailed information. Host Interface The MSM7712 meets the timing requirements of the PCMCIA interface. Wait states are used to provide the access times to the shared RAM when required. Shared Memory Interface The shared memory cycle time is 2 RCK clock periods. When the memory interface is not active the data bus RD[15:0] is output (low). This ensures the shared memory data bus does not float and consume power. 1. RCK at 16 MHz. Shared Memory Timing [1] Parameter Description Min. Typ. Max. Unit tS(RCE) Setup time of address, WR strobe and data output to RCE asserted 20 - - ns tH(RCE) Hold time of address, WR strobe and data output to RCE deasserted 10 - - tRCE RCE low period (with 16/32 MHz SCK) 85 - - tS(D-CE) Setup time of read data to RCE deasserted 10 - - tACC RAM access time Tce -Ts (d-rce) 75 - - tH(RCE-D) Hold time of read data to RCE deasserted 0 - - tH(CYC) Hold time before data bus driven low 50 - 70 Figure 6. Shared Memory Timing RA[], RWRN RCEHN, RCELN RD[], READ RD[], WRITE TS(RCE) TRCE TB(RCE) TS(D-RCE) TH(RCE-D) TH(CYC) |
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