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IC41LV1665-30K Datasheet(PDF) 7 Page - Integrated Circuit Solution Inc

Part # IC41LV1665-30K
Description  64K x16 bit Dynamic RAM with Fast Page Mode
Download  19 Pages
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Manufacturer  ICSI [Integrated Circuit Solution Inc]
Direct Link  http://www.icsi.com.tw
Logo ICSI - Integrated Circuit Solution Inc

IC41LV1665-30K Datasheet(HTML) 7 Page - Integrated Circuit Solution Inc

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IC41C1665
IC41LV1665
Integrated Circuit Solution Inc.
7
DR031-0A 10/17/2001
ELECTRICAL CHARACTERISTICS(1) (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
IIL
Input Leakage Current
Any input 0V
≤ VIN ≤ Vcc
–10
10
µA
Other inputs not under test = 0V
IIO
Output Leakage Current
Output is disabled (Hi-Z)
–10
10
µA
0V
≤ VOUT ≤ Vcc
VOH
Output High Voltage Level
IOH = –5 mA
2.4
V
VOL
Output Low Voltage Level
IOL = +4.2 mA
0.4
V
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
5V
2
mA
mA
ICC1
Stand-by Current: TTL
RAS, LCAS, UCAS ≥ VIH
3.3V
1
mA
mA
ICC2
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
5V
1
mA
ICC2
Stand-by Current: CMOS
RAS, LCAS, UCAS ≥ VCC – 0.2V
3.3V
0.5
mA
ICC3
Operating Current:
RAS, LCAS, UCAS,
-25
170
mA
Random Read/Write(2,3,4)
Address Cycling, tRC = tRC (min.)
-30
150
Average Power Supply Current
-35
130
-40
120
ICC4
Operating Current:
RAS = VIL, LCAS, UCAS,
-25
170
mA
Fast Page Mode(2,3,4)
Cycling tPC = tPC (min.)
-30
150
Average Power Supply Current
-35
130
-40
120
ICC5
Refresh Current:
RAS Cycling, LCAS, UCAS ≥ VIH
-25
170
mA
RAS-Only(2,3)
tRC = tRC (min.)
-30
150
Average Power Supply Current
-35
130
-40
120
ICC6
Refresh Current:
RAS, LCAS, UCAS Cycling
-25
170
mA
CBR(2,3,5)
tRC = tRC (min.)
-30
150
Average Power Supply Current
-35
130
-40
120
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS refresh cycles (RAS-Only or CBR) before proper
device operation is assured.The eight
RAS cycles wake-up should be repeated any time the tREF refresh requirement is
exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each fast page cycle.
5. Enables on-chip refresh and address counters.


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