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CYM1836
4
Switching Characteristics Over the Operating Range[4]
Parameter
Description
1836–15
1836–20
1836–25
1836–30
1836–35
1836– 45
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
15
20
25
30
35
45
ns
tAA
Address to Data
Valid
15
20
25
30
35
45
ns
tOHA
Output Hold from
Address Change
3
3
3
3
3
3
ns
tACS
CS LOW to Data
Valid
15
20
25
30
35
45
ns
tDOE
OE LOW to Data
Valid
7
8
8
10
12
15
ns
tLZOE
OE LOW to
Low Z
0
0
0
0
0
0
ns
tHZOE
OE HIGH to High
Z
7
8
10
11
12
15
ns
tLZCS
CS LOW to
Low Z[5]
3
3
3
3
3
3
ns
tHZCS
CS HIGH to High
Z[5, 6]
7
10
10
13
15
18
ns
WRITE CYCLE[7]
tWC
Write Cycle Time
15
20
25
30
35
45
ns
tSCS
CS LOW to Write
End
12
15
15
18
20
25
ns
tAW
Address Set-Up
to Write End
12
15
15
18
20
25
ns
tHA
Address Hold
from Write End
0
0
0
0
0
0
ns
tSA
Address Set-Up
to Write Start
0
0
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
18
20
25
ns
tSD
Data Set-Up to
Write End
7
10
10
13
15
20
ns
tHD
Data Hold from
Write End
0
0
0
0
0
0
ns
tLZWE
WE HIGH to Low
Z
3
3
3
3
3
3
ns
tHZWE
WE LOW to High
Z[6]
0
6
0
8
0
10
0
15
0
15
0
18
ns
Shaded area contains preliminary information.
Notes:
4.
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. These parameters are guaranteed by design and not 100% tested.
6.
tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
7.
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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