VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

9/6/00

G52251-0, Rev. 4.0

Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs

Receiver Low-Speed Interface

The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface

155.52MHz.

The RXCLK16O and RXCLK16_32O output drivers are designed to drive a 50

Ω transmission line. The

transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by

50

Ω to V

illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for

AC-coupling. The divide-by-16 output (RXCLK16O) or the divide-by-16 or -32 output (RXCLK16_32O) can

be used to provide an external looptiming reference clock (after external filtering with a 1x REFCLK PLL) for

the clock multiplication unit on the VSC8140.

The RXOUT[15:0] output drivers are designed to drive a 50

Ω transmission line which can be DC termi-

nated with a split-end termination scheme (see Figure 6), or a traditional termination scheme (see Figure 7).

Figure 6: Split-end DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs

VSC8140

100nF

50

Ω

50

Ω

100nF

downstream

bias point

generated

internally

VSC8140

R1 = 125

Ω

R2 = 83

Ω

R1 = 125

Ω R2 = 83Ω, Z

R1+R2