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VSC8140 Datasheet(PDF) 4 Page - Vitesse Semiconductor Corporation |
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VSC8140 Datasheet(HTML) 4 Page - Vitesse Semiconductor Corporation |
4 / 34 page VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8140 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator Page 4 © VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 9/6/00 G52251-0, Rev. 4.0 Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs Receiver Low-Speed Interface The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface RXOUT[15:0] with accompanying differential LVPECL divide-by-16 clock RXCLK16O± and selectable LVPECL divide-by-16 or -32 clock RXCLK16_32O±. RXCLKO_FREQSEL is used to select RXCLK16_32O±. RXCLKO_FREQSEL = “0” designates RXCLK16_32O± output as 77.76MHz, RXCLKO_FREQSEL = “1” designates RXCLK16_32O± output as 155.52MHz. The RXCLK16O and RXCLK16_32O output drivers are designed to drive a 50 Ω transmission line. The transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by 50 Ω to V CC-2V on each line (see Figure 4). AC-coupling can be achieved by a number of methods. Figure 5 illustrates an AC-coupling method for the occasion when the downstream device provides the bias point for AC-coupling. The divide-by-16 output (RXCLK16O) or the divide-by-16 or -32 output (RXCLK16_32O) can be used to provide an external looptiming reference clock (after external filtering with a 1x REFCLK PLL) for the clock multiplication unit on the VSC8140. The RXOUT[15:0] output drivers are designed to drive a 50 Ω transmission line which can be DC termi- nated with a split-end termination scheme (see Figure 6), or a traditional termination scheme (see Figure 7). Figure 6: Split-end DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs VSC8140 100nF 50 Ω 50 Ω Zo Zo 100nF VCC-2V downstream bias point generated internally VSC8140 Zo R1 = 125 Ω VEE VCC R2 = 83 Ω Split-end equivalent termination is ZO to VTERM R1 = 125 Ω R2 = 83Ω, Z O=50Ω, VTERM= VCC-2V VCCR2 + VEER1 R1+R2 = VTERM R1||R2 = Zo |
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