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PGA2320IDWRG4 Datasheet(PDF) 8 Page - Texas Instruments

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Part # PGA2320IDWRG4
Description  Stereo Audio Volume Control
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PGA2320IDWRG4 Datasheet(HTML) 8 Page - Texas Instruments

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PGA2320
SBOS312B − JULY 2004 − REVISED DECEMBER 2004
www.ti.com
8
SERIAL CONTROL PORT
The serial control port is utilized to program the gain
settings for the PGA2320. The serial control port includes
three input pins and one output pin. The inputs include CS
(pin 2), SDI (pin 3), and SCLK (pin 6). The sole output pin
is SDO (pin 7).
The CS pin functions as the chip select input. Data may be
written to the PGA2320 only when CS is low. SDI is the
serial data input pin. Control data is provided as a 16-bit
word at the SDI pin, 8 bits each for the left and right channel
gain settings. Data is formatted as MSB first, straight
binary code. SCLK is the serial clock input. Data is clocked
into SDI on the rising edge of SCLK.
SDO is the serial data output pin, and is used when
daisy-chaining multiple PGA2320 devices. Daisy-chain
operation is described in detail later in this section. SDO
is a tristate output, and assumes a high impedance state
when CS is high.
The protocol for the serial control port is shown in Figure 2.
See Figure 3 for detailed timing specifications of the serial
control port.
Gain Byte Format is MSB First, Straight Binary
R0 is the Least Significant Bit of the Right Channel Gain Byte
R7 is the Most Significant Bit of the Right Channel Gain Byte
L0 is the Least Significant Bit of the Left Channel Gain Byte
L7 is the Most Significant Bit of the Left Channel Gain Byte
SDI is latched on the rising edge of SCLK
SDO transitions on the falling edge of SCLK
CS
SCLK
SDI
SDO
R6
R5
R4
R3
R2
R1
R0
L7
L6
L5
L4
L3
L2
L1
L0
R7
R7
R6
R5
R4
R3
R2
R1
R0
L7
L6
L5
L4
L3
L2
L1
L0
Figure 2. Serial Interface Protocol


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