KS7332

13

MICOM REGISTER TABLE

OPERATION DESCRIPTION

The start signal and clock operate in slave mode, so this part is nonsychronous to the rest of the system. The

register setting is normally carried out for all segments within the field, and it is latched at negedge VD when scsn

is restored to high.

Figure 4. Operation Description

Symbol

Description

Standard (

µs)

min

max

td1

SCSN low edge to SCLK low edge

0.2

-

td2

SCLK high edge to SCSN high edge

0.2

-

thw

SCLK high width

0.2

-

tlw

SCLK low width

0.2

-

tsu

SI data setup time

0.2

-

thd

SI data hold time

0.2

-

tdo

SO data out delay time

-

0.1

td2

SCSN

SCLK

SI

SO

si_data[255]

si_data[254]

si_data[0]

so_data[255] so_data[254]

so_data[0]

td1

thw

tlw

tdo

tsu

thd