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ISP1161ABD Datasheet(PDF) 89 Page - NXP Semiconductors

Part # ISP1161ABD
Description  Full-speed Universal Serial Bus single-chip host and device controller
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

ISP1161ABD Datasheet(HTML) 89 Page - NXP Semiconductors

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Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
89 of 134
9397 750 13962
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
the DcDMACounter register. When the internal counter completes the transfer as
programmed in the DcDMACounter, an EOT condition is generated and the DMA
operation stops.
Short packet: Normally, the transfer byte count must be set via a control endpoint
before any DMA transfer takes place. When a short packet has been enabled as EOT
indicator (SHORTP = 1), the transfer size is determined by the presence of a short
packet in the data. This mechanism permits the use of a fully autonomous data
transfer protocol.
When reading from an OUT endpoint, reception of a short packet at an OUT token
will stop the DMA operation after transferring the data bytes of this packet.
[1]
The DMA transfer stops. However, no interrupt is generated.
12.4.2
Isochronous endpoints
A DMA transfer to/from an isochronous endpoint can be terminated by any of the
following conditions (bit names refer to the DcDMAConfiguration register, see
Table 86):
An external End-Of-Transfer signal occurs on input EOT
The DMA transfer completes as programmed in the DcDMACounter register
(CNTREN = 1)
An End-Of-Packet (EOP) signal is detected
DMA operation is disabled by clearing bit DMAEN.
Table 73:
Summary of EOT conditions for a bulk endpoint
EOT condition
OUT endpoint
IN endpoint
EOT input
EOT is active
EOT is active
DcDMACounter register
transfer completes as
programmed in the
DcDMACounter register
transfer completes as
programmed in the
DcDMACounter register
Short packet
short packet is received and
transferred
counter reaches zero in the
middle of the buffer
DMAEN bit in
DcDMAConfiguration register
DMAEN = 0[1]
DMAEN = 0[1]
Table 74:
Recommended EOT usage for isochronous endpoints
EOT condition
OUT endpoint
IN endpoint
EOT input active
do not use
preferred
DMA Counter register zero
do not use
preferred
End-Of-Packet
preferred
do not use


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