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ISP1161ABD Datasheet(PDF) 39 Page - NXP Semiconductors |
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ISP1161ABD Datasheet(HTML) 39 Page - NXP Semiconductors |
39 / 134 page Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Product data Rev. 03 — 23 December 2004 39 of 134 9397 750 13962 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9.8 OC detection and power switching control A downstream port provides 5 V power supply to VBUS. The ISP1161A has built-in hardware functions to monitor the downstream ports loading conditions and control their power switching. These hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit. H_PSW1 and H_PSW2 are power switching control output pins (active LOW, open drain) for downstream port 1 and 2, respectively. H_OC1 and H_OC2 are overcurrent detection input pins for downstream ports 1 and 2, respectively. Figure 34 shows the ISP1161A downstream port power management scheme (‘n’ represents the downstream port numbers, n=1or2). Using either internal or external 15 k Ω resistors. Fig 33. Use of 15 k Ω pull-down resistors on downstream ports. 004aaa088 22 Ω 22 Ω bit 12 HcHardware Configuration ISP1161A USB connector D − D + VBUS internal 15 k Ω (2 ×) external 15 k Ω (2 ×) 47 pF (2 ×) ‘n’ represents the downstream port number (n=1or2) Fig 34. Downstream port power management scheme. 004aaa089 1 ≥ 0 Reg bit 10 PSW OC select OC detect regulator H_OCn H_PSWn HC CORE C/L ISP1161A VCC ( +5 V or +3.3 V) HcHardware Configuration |
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