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ISP1161A Datasheet(PDF) 58 Page - NXP Semiconductors |
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ISP1161A Datasheet(HTML) 58 Page - NXP Semiconductors |
58 / 134 page Philips Semiconductors ISP1161A Full-speed USB single-chip host and device controller Product data Rev. 03 — 23 December 2004 58 of 134 9397 750 13962 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Code (Hex): 13 — read Code (Hex): 93 — write Table 30: HcRhDescriptorB register: bit allocation Bit 31 30 29 28 27 26 25 24 Symbol reserved Reset N/A N/A N/A N/A N/A N/A N/A N/A Access RRRRRRRR Bit 23 22 21 20 19 18 17 16 Symbol reserved PPCM[2:0] Reset N/A N/A N/A N/A N/A IS IS IS Access RRRRR R/W R/W R/W Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset N/A N/A N/A N/A N/A N/A N/A N/A Access RRRRRRRR Bit 7 6 5 4 3 2 1 0 Symbol reserved DR[2:0] Reset N/A N/A N/A N/A N/A IS IS IS Access RRRRR R/W R/W R/W Table 31: HcRhDescriptorB register: bit description Bit Symbol Description 31 to 19 - reserved 18 to 16 PPCM[2:0] PortPowerControlMask: Each bit indicates whether a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port’s power state is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode = 0), this field is not valid. Bit 0 — reserved Bit 1 — Ganged-power mask on Port #1 Bit 2 — Ganged-power mask on Port #2 |
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