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N682387YG Datasheet(PDF) 96 Page - Nuvoton Technology Corporation |
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N682387YG Datasheet(HTML) 96 Page - Nuvoton Technology Corporation |
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96 / 160 page  N682386/87 + N681622 Dual Programmable Extended Codec/SLCC + SLFC Revision 1.3 Page 96 of 160 Sep 2010 14.5.3. INTERRUPT ENABLE REGISTER 1 Addr Name D7 D6 D5 D4 D3 D2 D1 D0 Default 0x27 IE1 PAT3ECn PAR3ECn PAT1ECn PAR1ECn PAR2ECn PAT2ECn LCECn RTECn 0x00 The letters “Cn” stands for channel number 1 or 2. This register enables all the Power Alarm and the Loop Closure interrupt of the device. An interrupt can be enabled by writing a HIGH “1” in the respective interrupt bit. Bit Location Bit Description Bit Name Bit Value 0 1 0 RING Trip RTECn Masked Enabled 1 Loop Closure LCECn Masked Enabled 2 Power Alarm QR2 PAT2ECn Masked Enabled 3 Power Alarm QT2 PAR2ECn Masked Enabled 4 Power Alarm QT1 PAR1ECn Masked Enabled 5 Power Alarm QR1 PAT1ECn Masked Enabled 6 Power Alarm QR3 PAR3ECn Masked Enabled 7 Power Alarm QT3 PAT3ECn Masked Enabled 14.5.4. INTERRUPT STATUS REGISTER 2 Addr. Name D7 D6 D5 D4 D3 D2 D1 D0 Default 0x28 INT2 FSKICn DTMFICn RICn RACn O2ICn O2ACn O1ICn O1ACn 0x00 The letters “Cn” stands for channel number 1 or 2. Bit Location Bit Description Bit Name Bit Value 0 1 0 Oscillator 1 Active Timer O1ACn No INT INT Pending 1 Oscillator 1 Inactive Timer O1ICn No INT INT Pending 2 Oscillator 2 Active Timer O2ACn No INT INT Pending 3 Oscillator 2 Inactive Timer O2ICn No INT INT Pending 4 Ringing Active Timer RACn No INT INT Pending 5 Ringing Inactive Timer RICn No INT INT Pending 6 DTMF Initialize DTMFICn No INT INT Pending 7 FSK Interrupt occurs when the FSK FIFO is empty FSKICn No INT INT Pending |
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