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N682387MG Datasheet(PDF) 83 Page - Nuvoton Technology Corporation |
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N682387MG Datasheet(HTML) 83 Page - Nuvoton Technology Corporation |
83 / 160 page N682386/87 + N681622 Dual Programmable Extended Codec/SLCC + SLFC Revision 1.3 Page 83 of 160 Sep 2010 14.1.4. PCM FREQUENCY SETTING REGISTER Addr. Name D7 D6 D5 D4 D3 D2 D1 D0 Default Shared Async (D7- D1) 0x05 PCMFS BCF[3:0] IFST FSS WBENCn SRES 0x00 The following table explains the PCM Frequency Setting register bits. Bit Location Bit Description Bit Name Bit Value 0 1 0 Soft Reset SRES Disable Enable 1 Band Select WBENCn FS = 8kHz (Narrowband) FS = 16kHz (Wideband) 2 Frame Sync Source FSS External Internal 3 Internal Frame Sync Type IFST Short (fixed width 1 BCLK) Long (fixed width 8 BCLK) When an internal 8 kHz Frame Sync is used (PCMFS:FSS=1) these bits should be programmed with the value of BCLK Frequency, BCFS[3:0], according to the following table. Bit Clock Frequency BCF [4] BCF [3] BCF [2] BCF [1] BCLK (Hz) 0 0 0 0 256 0 0 0 1 512 0 0 1 0 768 0 0 1 1 1000 0 1 0 0 1024 0 1 0 1 1152 0 1 1 0 1536 0 1 1 1 1544 1 0 0 0 2000 1 0 0 1 2048 1 0 1 0 4000 1 0 1 1 4096 1 1 0 0 8000 1 1 0 1 8192 1 1 1 0 NA 1 1 1 1 |
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