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CY7C107B
CY7C1007B
Document #: 38-05030 Rev. **
Page 4 of 9
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1 480
Ω
R2
255
Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3 ns
≤ 3 ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
R2
255
Ω
R1 480
Ω
167
Ω
107-3
107-4
Switching Characteristics[5] Over the Operating Range
7C107B-12
7C1007B-12
7C107B-15
7C1007B-15
7C107B-20
7C1007B-20
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
15
20
25
35
ns
tAA
Address to Data Valid
12
15
20
25
35
ns
tOHA
Data Hold from Address
Change
3
3
333
ns
tACE
CE LOW to Data Valid
12
15
20
25
35
ns
tLZCE
CE LOW to Low Z[6]
3
3
333
ns
tHZCE
CE HIGH to High Z[6, 7]
67
8
10
10
ns
tPU
CE LOW to Power-Up
0
0
0
0
0
ns
tPD
CE HIGH to Power-Down
12
15
20
25
35
ns
WRITE CYCLE[8]
tWC
Write Cycle Time
12
15
20
25
35
ns
tSCE
CE LOW to Write End
10
12
15
20
25
ns
tAW
Address Set-Up to Write
End
10
12
15
20
25
ns
tHA
Address Hold from Write
End
0
0
000
ns
tSA
Address Set-Up to Write
Start
0
0
000
ns
tPWE
WE Pulse Width
10
12
15
20
25
ns
tSD
Data Set-Up to Write End
7
8
10
15
20
ns
tHD
Data Hold from Write End
0
0
0
0
0
ns
tLZWE
WE HIGH to Low Z[6]
3
3
333
ns
tHZWE
WE LOW to High Z[6, 7]
67
8
10
10
ns
Notes:
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6.
At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device.
7.
tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8.
The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
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