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DSM2180F315K6 Datasheet(PDF) 10 Page - STMicroelectronics |
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DSM2180F315K6 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 63 page DSM2180F3 10/63 Table 3. Pin Description Pin Name Type Description ADIO0-15 In Sixteen address inputs from the DSP. CNTL0 In Active low write strobe input (WR) from the DSP CNTL1 In Active low read strobe input (RD) from the DSP. CNTL2 In Active low Byte Memory Select (BMS) signal from the DSP. Reset In Active low reset input from system. Resets DSM I/O Ports, Page Register contents, and other DSM configuration registers. Must be logic Low at Power-up. PA0-7 I/O Eight data bus signals connected to DSP pins D8 - D15. PB0-7 I/O Eight configurable Port B signals with the following functions: 1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers. 2. CPLD Output Macrocell (McellAB0-7 or McellBC0-7) outputs. 3. Inputs to the PLDs (Input Macrocells). Note: Each of the four Port B signals PB0-PB3 may be configured at run-time as either standard CMOS or for high slew rate. Each of the four Port B signals PB3-PB7 may be configured at run-time as either standard CMOS or Open Drain Outputs. PC0-7 I/O Eight configurable Port C signals with the following functions: 1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers. 2. CPLD Output Macrocell (McellBC0-7) output. 3. Input to the PLDs (Input Macrocells). 4. Pins PC0, PC1, PC5, and PC6 can optionally form the JTAG IEEE-1149.1 ISP serial interface as signals TMS, TCK, TDI, and TDO respectively. 5. Pins PC3 and PC4 can optionally form the enhanced JTAG signals TSTAT and TERR respectively. Reduces ISP programming time by up to 30% when used in addition to the standard four JTAG signals: TDI, TDO, TMS, TCK. 6. Pin PC3 can optionally be configured as the Ready/Busy output to indicate Flash memory programming status during parallel programming. May be polled by DSP or used as DSP interrupt to indicate when Flash memory byte programming or erase operations are complete. Note 1: Port C pin PC2 input (or any PLD input pin) can be connected to DSP D18 output which functions as DSP address A16 in DSP Full Memory Mode. See Figure 6. Note 2: Port C pin PC7 input (or any PLD input pin) can be connected to DSP D19 output which functions as DSP address A17 in DSP Full Memory Mode. See Figure 6. Note 3: When used as general I/O, each of the eight Port C signals may be configured at run-time as either standard CMOS or Open Drain Outputs. Note 4: The JTAG ISP pins may be multiplexed with other I/O functions. PD0-2 I/O Three configurable Port D signals with the following functions: 1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers. 2. Input to the PLDs (no associated Input Macrocells, routes directly into PLDs). 3. CPLD output (External Chip Select). Does not consume Output Macrocells. 4. Pin PD1 can optionally be configured as CLKIN, a common clock input to PLD. 5. Pin PD2 can optionally be configured as CSI, an active low Chip Select Input to select Flash memory. Flash memory is disabled to conserve more power when CSI is logic high. Can connect CSI to ADSP-218X PWDACK output signal. Note 1: It is recommended to connect Port D pin PD0 input to DSP IOMS output which is the active low I/O Memory Select strobe. See Figure 6. Note 2: It is recommended to connect Port D pin PD1 input to DSP DMS output which is the active low Data Memory Select strobe. See Figure 6. Note 3: It is recommended to connect Port D pin PD2 input to DSP PWDACK output if the DSP Power Down mode is used. See Figure 6. VCC Supply Voltage GND Ground pins |
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